1640 search results - page 63 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
102
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JPDC
2011
14 years 9 months ago
2011
Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors. Because messages compete for the NoC’s shared resources, quality of service and resource ...
ISCAS
2006
IEEE
15 years 8 months ago
2006
IEEE
Abstract— A fast timing analysis of plane circuits via two-layer CNNbased modeling, which is necessary for the solution of power/signal integrity problems in printed circuit boar...
128
Voted
SOPR
2002
15 years 2 months ago
2002
Good project scheduling is an essential, but extremely hard task in software management practice. In a software project, the time needed to complete some development activity is d...
118
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APNOMS
2006
Springer
15 years 6 months ago
2006
Springer
Time-Slotted Optical Burst Switching (TS-OBS) is one of the most promising next-generation transport network technologies. This paper proposes a time-slot assignment procedure usin...
117
Voted
SASP
2008
IEEE
15 years 8 months ago
2008
IEEE
This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The proces...