1640 search results - page 74 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
152
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CASES
2008
ACM
15 years 4 months ago
2008
ACM
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...
134
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ISORC
1998
IEEE
15 years 6 months ago
1998
IEEE
Many engineers are still reluctant to adopt advanced object-oriented technologies (such as high modularity, dynamic binding, automatic garbage collection, etc.) for embedded syste...
105
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CORR
2007
Springer
15 years 2 months ago
2007
Springer
In this paper we analyse the requirements of performing parallel transaction-oriented simulations within loosely coupled systems like Ad Hoc Grids. We focus especially on the spac...
133
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APSEC
2002
IEEE
15 years 7 months ago
2002
IEEE
We present a discrete simulation model for software projects which explicitly takes a scheduling strategy as input. The model represents varying staff skill levels, component coup...
122
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AINA
2007
IEEE
15 years 9 months ago
2007
IEEE
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...