Sciweavers

1640 search results - page 78 / 328
» Transistor-Level Timing Analysis Using Embedded Simulation
Sort
View
ASPDAC
2005
ACM
153views Hardware» more  ASPDAC 2005»
15 years 4 months ago
Design of clocked circuits using UML
– Clocking is an essential component of any embedded system design. However, traditional design techniques are either short of clocking support or too complex for users. The Unif...
Zhenxin Sun, Weng-Fai Wong, Yongxin Zhu, Santhosh ...
120
Voted
ECRTS
2007
IEEE
15 years 9 months ago
Memory Resource Management for Real-Time Systems
Dynamic memory storage has been widely used for years in computer science. However, its use in real-time systems has not been considered as an important issue, and memory manageme...
Audrey Marchand, Patricia Balbastre, Ismael Ripoll...
129
Voted
ECRTS
2004
IEEE
15 years 6 months ago
Maintaining Data Freshness in Distributed Real-Time Databases
Many real-time systems need to maintain fresh views which are derived from shared data that are distributed among multiple sites. When a base data item changes, all derived views ...
Yuan Wei, Sang Hyuk Son, John A. Stankovic
JSAC
2006
103views more  JSAC 2006»
15 years 2 months ago
Performance analysis of M-ary PPM TH-UWB systems in the presence of MUI and timing jitter
The symbol error probability (SEP) performance of time-hopping (TH) ultra-wideband (UWB) systems in the presence of multiuser interference (MUI) and timing jitter is considered wit...
N. V. Kokkalis, P. Takis Mathiopoulos, George K. K...
128
Voted
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
15 years 6 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko