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» Transistor-Level Timing Analysis Using Embedded Simulation
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PE
2008
Springer
173views Optimization» more  PE 2008»
15 years 2 months ago
M/G/1 queue with deterministic reneging times
We consider single-server and multi-server queues with deterministic reneging times motivated by the timeout mechanisms used in application servers.. A Volterra integral equation ...
Wei Xiong, David L. Jagerman, Tayfur Altiok
100
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DATE
2007
IEEE
92views Hardware» more  DATE 2007»
15 years 9 months ago
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller ...
Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Ch...
116
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HYBRID
2009
Springer
15 years 6 months ago
Trajectory Based Verification Using Local Finite-Time Invariance
Abstract. In this paper we propose a trajectory based reachability analysis by using local finite-time invariance property. Trajectory based analysis are based on the execution tra...
A. Agung Julius, George J. Pappas
110
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SAS
2001
Springer
121views Formal Methods» more  SAS 2001»
15 years 7 months ago
Embedding Chaos
Model checking would answer all finite-state verification problems, if it were not for the notorious state-space explosion problem. A problem of practical importance, which attra...
Natalia Sidorova, Martin Steffen
123
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ISOLA
2010
Springer
15 years 1 months ago
Ten Years of Performance Evaluation for Concurrent Systems Using CADP
This article comprehensively surveys the work accomplished during the past decade on an approach to analyze concurrent systems qualitatively and quantitatively, by combining functi...
Nicolas Coste, Hubert Garavel, Holger Hermanns, Fr...