1640 search results - page 83 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
134
Voted
QEST
2010
IEEE
15 years 14 days ago
2010
IEEE
The method of stochastic state classes approaches the analysis of Generalised Semi Markov Processes (GSMP) through symbolic derivation of probability density functions over Differe...
92
Voted
ICRA
2007
IEEE
15 years 9 months ago
2007
IEEE
Abstract— In this paper, we propose a new approach to wireless sensor network assisted navigation while avoiding moving dangers. Our approach relies on an embedded roadmap in the...
129
Voted
JEC
2006
15 years 2 months ago
2006
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
124
Voted
WSC
1998
1998
Effective Implementation of Cycle Time Reduction Strategies for Semiconductor Back-end Manufacturing
15 years 4 months ago
Using discrete-event simulation models, a study was conducted to evaluate the current production practices of a high-volume semiconductor back-end operation. The overall goal was ...
109
Voted
ICCAD
1999
IEEE
15 years 7 months ago
1999
IEEE
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...