1640 search results - page 86 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
121
Voted
ASPDAC
2006
ACM
15 years 8 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
108
click to vote
DATE
2006
IEEE
15 years 8 months ago
2006
IEEE
This paper focuses on statistical interconnect timing analysis in a parameterized block-based statistical static timing analysis tool. In particular, a new framework for performin...
128
Voted
ICCAD
2003
IEEE
15 years 8 months ago
2003
IEEE
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
116
Voted
TCOM
2008
15 years 2 months ago
2008
In this paper we develop a fine synchronization algorithm for multiband OFDM transmission in the presence of frequency selective channels. This algorithm is based on maximum a post...
95
Voted
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
—The advanced sampling and variance reduction techniques as efficient alternatives to the slow crude-MC method have recently been adopted for the analysis of timing yield in dig...