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CADE
2006
Springer
16 years 2 months ago
CEL - A Polynomial-Time Reasoner for Life Science Ontologies
CEL (Classifier for EL) is a reasoner for the small description logic EL+ which can be used to compute the subsumption hierarchy induced by EL+ ontologies. The most distinguishing ...
Franz Baader, Carsten Lutz, Boontawee Suntisrivara...
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
15 years 8 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
TAP
2008
Springer
102views Hardware» more  TAP 2008»
15 years 1 months ago
Visualizing graphs in three dimensions
It has been known for some time that larger graphs can be interpreted if laid out in 3D and displayed with stereo and/or motion depth cues to support spatial perception. However, ...
Colin Ware, Peter Mitchell
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
15 years 10 months ago
Design and Implementation of Software Objects in Hardware
This paper proposes a novel approach to implement software object in hardware. Data-Memory mapping schemes are investigated and four hardware object design schemes are proposed an...
Fu-Chiung Cheng, Hung-Chi Wu
ICCD
2004
IEEE
105views Hardware» more  ICCD 2004»
15 years 10 months ago
Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation
In this paper we discuss the application of circuit-based logical reasoning to simplify optimization problems expressed as integer linear programs (ILP) over circuit states. We de...
Donald Chai, Andreas Kuehlmann