Sciweavers

8 search results - page 1 / 2
» Treegion Scheduling for Wide Issue Processors
Sort
View
HPCA
1998
IEEE
15 years 2 months ago
Treegion Scheduling for Wide Issue Processors
William A. Havanki, Sanjeev Banerjia, Thomas M. Co...
ISCA
2003
IEEE
150views Hardware» more  ISCA 2003»
15 years 3 months ago
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Dan Ernst, Andrew Hamel, Todd M. Austin
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
15 years 2 months ago
Circuits for wide-window superscalar processors
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh...
RTSS
2007
IEEE
15 years 4 months ago
Generalized Tardiness Bounds for Global Multiprocessor Scheduling
We consider the issue of deadline tardiness under global multiprocessor scheduling algorithms. We present a general tardiness-bound derivation that is applicable to a wide variety...
Hennadiy Leontyev, James H. Anderson
SAC
2010
ACM
14 years 11 months ago
Energy-efficient scheduling on homogeneous multiprocessor platforms
Low-power and energy-efficient system implementations have become very important design issues to extend operation duration or cut power bills. To balance the energy consumption r...
Jian-Jia Chen, Lothar Thiele