87 search results - page 10 / 18 » Trends and techniques for energy efficient architectures |
109
click to vote
HPCA
2008
IEEE
16 years 2 days ago
2008
IEEE
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe...
FPL
2007
Springer
15 years 5 months ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
122
click to vote
ISCAPDCS
2007
15 years 1 months ago
2007
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
DATE
2004
IEEE
15 years 3 months ago
2004
IEEE
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
ICCD
2002
IEEE
15 years 8 months ago
2002
IEEE
Fault-tolerant distributed real-time systems are presently facing a lot of new challenges. Although many techniques provide effective masking of node failures on the architectural...