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» Trends and techniques for energy efficient architectures
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DAC
2004
ACM
13 years 10 months ago
Enabling energy efficiency in via-patterned gate array devices
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architecture...
R. Reed Taylor, Herman Schmit
ARITH
2007
IEEE
13 years 10 months ago
Robust Energy-Efficient Adder Topologies
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determi...
Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, R...
VLSID
2004
IEEE
112views VLSI» more  VLSID 2004»
14 years 6 months ago
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization
It has been observed that even highly optimized software programs perform "redundant" computations during their execution, due to the nature (statistics) of the values a...
Weidong Wang, Anand Raghunathan, Niraj K. Jha
FPL
2004
Springer
144views Hardware» more  FPL 2004»
13 years 10 months ago
A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementin...
Jingzhao Ou, Viktor K. Prasanna
CONEXT
2009
ACM
13 years 7 months ago
Cool-Tether: energy efficient on-the-fly wifi hot-spots using mobile phones
We consider the problem of providing ubiquitous yet affordable Internet connectivity to devices at home, at work, and on the move. In this context, we take advantage of two signif...
Ashish Sharma, Vishnu Navda, Ramachandran Ramjee, ...