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CAMP
2000
IEEE
15 years 8 months ago
An FPGA Architecture for High Speed Edge and Corner Detection
This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per sec...
Cesar Torres-Huitzil, Miguel Arias-Estrada
HPCA
2008
IEEE
16 years 4 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
JUCS
2000
135views more  JUCS 2000»
15 years 4 months ago
The Price of Routing in FPGAs
: Studying the architectural evolution of mainstream field programmable gate arrays (FPGAs) leads to the following remark: in these circuits, the proportion of silicon devoted to r...
Florent de Dinechin
WIOPT
2010
IEEE
15 years 2 months ago
Performance tuning of Infrastructure-Mode wireless LANs
—Conventional wisdom about 802.11 WLANs dictates that as the number of active users increases, the contention windows (CW) of all the contending users needs to increase to preven...
Yigal Bejerano, Hyoung-Gyu Choi, Seung-Jae Han, Th...
RECONFIG
2008
IEEE
122views VLSI» more  RECONFIG 2008»
15 years 10 months ago
Using a CSP Based Programming Model for Reconfigurable Processor Arrays
The growing trend towards adoption of flexible and heterogeneous, parallel computing architectures has increased the challenges faced by the programming community. We propose a me...
Zain-ul-Abdin, Bertil Svensson