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ERSA
2008
185views Hardware» more  ERSA 2008»
14 years 11 months ago
Design Framework for Partial Run-Time FPGA Reconfiguration
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
Chris Conger, Ann Gordon-Ross, Alan D. George
TC
2008
14 years 9 months ago
High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware
Numerical linear algebra operations are key primitives in scientific computing. Performance optimizations of such operations have been extensively investigated. With the rapid adva...
Ling Zhuo, Viktor K. Prasanna
SBCCI
2006
ACM
171views VLSI» more  SBCCI 2006»
15 years 3 months ago
Asynchronous circuit design on reconfigurable devices
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, An...
SAC
2003
ACM
15 years 3 months ago
ARCHITECT-R: A System for Reconfigurable Robots Design
An increasing interest in the design of mobile robots has been observed in recent years, which is mainly motivated by technological advances that may allow their application to co...
R. A. Gonçalves, P. A. Moraes, João ...
FPL
1997
Springer
78views Hardware» more  FPL 1997»
15 years 2 months ago
Run-time compaction of FPGA designs
Controllers for dynamically recon gurable FPGAs that are capable of supporting multiple independent tasks simultaneously need to be able to place designs at run{time when the seque...
Oliver Diessel, Hossam A. ElGindy