The increasing demand for FPGAs and reconfigurable hardware targeting high performance low power applications has lead to an increasing requirement for new high performance reconf...
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
ended abstract defines a class of architectures for pipeline reconfigurable FPGAs by parameterizing a generic model. This class of architectures is sufficiently general to allow e...
Trust management represents today a promising approach for supporting access control in open environments. While several approaches have been proposed for trust management and sig...
Sabrina De Capitani di Vimercati, Sushil Jajodia, ...