Sciweavers

3 search results - page 1 / 1
» Tuning Blocked Array Layouts to Exploit Memory Hierarchy in ...
Sort
View
92
Voted
PCI
2005
Springer
15 years 3 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
106
Voted
ICS
2007
Tsinghua U.
15 years 3 months ago
Adaptive Strassen's matrix multiplication
Strassen’s matrix multiplication (MM) has benefits with respect to any (highly tuned) implementations of MM because Strassen’s reduces the total number of operations. Strasse...
Paolo D'Alberto, Alexandru Nicolau
EUROPAR
2000
Springer
15 years 1 months ago
Cache Remapping to Improve the Performance of Tiled Algorithms
With the increasing processing power, the latency of the memory hierarchy becomes the stumbling block of many modern computer architectures. In order to speed-up the calculations, ...
Kristof Beyls, Erik H. D'Hollander