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» Two VLSI Design Advances in Arithmetic Coding
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ISJGP
2010
14 years 7 months ago
On the Hardware Implementation Cost of Crypto-Processors Architectures
A variety of modern technologies such as networks, Internet, and electronic services demand private and secure communications for a great number of everyday transactions. Security ...
Nicolas Sklavos
FCCM
1998
IEEE
113views VLSI» more  FCCM 1998»
15 years 2 months ago
PAM-Blox: High Performance FPGA Design for Adaptive Computing
PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC. High- performance FPGA design for adaptive computing is simplified by using a ...
Oskar Mencer, Martin Morf, Michael J. Flynn
VLSID
2010
IEEE
200views VLSI» more  VLSID 2010»
14 years 8 months ago
Pinpointing Cache Timing Attacks on AES
The paper analyzes cache based timing attacks on optimized codes for Advanced Encryption Standard (AES). The work justifies that timing based cache attacks create hits in the fi...
Chester Rebeiro, Mainack Mondal, Debdeep Mukhopadh...
CARDIS
2004
Springer
216views Hardware» more  CARDIS 2004»
15 years 3 months ago
Differential Fault Analysis Attack Resistant Architectures for the Advanced Encryption Standard
: We present two architectures for protecting a hardware implementation of AES against side-channel attacks known as Differential Fault Analysis attacks. The first architecture, wh...
Mark G. Karpovsky, Konrad J. Kulikowski, Alexander...
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...