524 search results - page 2 / 105 » Two efficient methods to reduce power and testing time |
SBCCI
2004
ACM
13 years 11 months ago
2004
ACM
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
TCAD
2010
13 years 1 months ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
DATE
2006
IEEE
14 years 12 days ago
2006
IEEE
1 This paper presents a test scheduling approach for system-onchip production tests with peak-power constraints. An abort-onfirst-fail test approach is assumed, whereby the test is...
BMCBI
2004
13 years 6 months ago
2004
Background: In a previous paper, we introduced MUSCLE, a new program for creating multiple alignments of protein sequences, giving a brief summary of the algorithm and showing MUS...
VTS
2008
IEEE
14 years 22 days ago
2008
IEEE
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...