628 search results - page 117 / 126 » Tying Memory Management to Parallel Programming Models |
ICS
2003
Tsinghua U.
15 years 3 months ago
2003
Tsinghua U.
Cache behavior modeling is an important part of modern optimizing compilers. In this paper we present a method to estimate the number of cache misses, at compile time, using a mac...
JRTIP
2008
14 years 10 months ago
2008
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
MICRO
2003
IEEE
15 years 3 months ago
2003
IEEE
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
ANCS
2007
ACM
15 years 2 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
CCGRID
2010
IEEE
14 years 11 months ago
2010
IEEE
Abstract--Multi-core processors with accelerators are becoming commodity components for high-performance computing at scale. While accelerator-based processors have been studied in...