628 search results - page 35 / 126 » Tying Memory Management to Parallel Programming Models |
HPCA
2007
IEEE
15 years 10 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
SPAA
2003
ACM
15 years 3 months ago
2003
ACM
Recent research on processor microarchitecture suggests using instruction criticality as a metric to guide hardware control policies. Fields et al. [3, 4] have proposed a directed...
IPPS
2008
IEEE
15 years 4 months ago
2008
IEEE
Transactional memory systems promise to reduce the burden of exposing thread-level parallelism in programs by relieving programmers from analyzing complex inter-thread dependences...
WSC
1997
14 years 11 months ago
1997
Components of modern parallel systems are becoming quite complex with many features and variations. An integrated modeling of these components (interconnection network, messaging ...
ISCA
1998
IEEE
15 years 1 months ago
1998
IEEE
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...