628 search results - page 70 / 126 » Tying Memory Management to Parallel Programming Models |
133
Voted
ASPLOS
1998
ACM
15 years 6 months ago
1998
ACM
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the sup...
103
Voted
IPPS
2002
IEEE
15 years 7 months ago
2002
IEEE
Future high-end computers will offer great performance improvements over today’s machines, enabling applications of far greater complexity. However, designers must solve the cha...
107
Voted
ICDCS
1991
IEEE
15 years 6 months ago
1991
IEEE
of ‘‘network computers’’ is inherently lessAbstract predictable than that of more traditional distributed memory systems, such as hypercubes [22], since both theFor computa...
195
Voted
HPDC
2008
IEEE
15 years 9 months ago
2008
IEEE
The emergence of heterogeneous many core architectures presents a unique opportunity for delivering order of magnitude performance increases to high performance applications by ma...
141
Voted
CF
2005
ACM
15 years 4 months ago
2005
ACM
Modern microprocessor designs continue to obtain impressive performance gains through increasing clock rates and advances in the parallelism obtained via micro-architecture design...