Sciweavers

628 search results - page 79 / 126
» Tying Memory Management to Parallel Programming Models
Sort
View
104
Voted
HPCA
1998
IEEE
15 years 2 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...
108
Voted
ISORC
2005
IEEE
15 years 3 months ago
Object-Reuse for More Predictable Real-Time Java Behavior
One of the problems with Java for real-time systems is the unpredictable behavior of garbage collection (GC). GC introduces unexpected load and causes undesirable delays for real-...
Jameela Al-Jaroodi, Nader Mohamed
85
Voted
HPCA
2005
IEEE
15 years 10 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
104
Voted
PLDI
2005
ACM
15 years 3 months ago
Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices
Speculative parallelization can provide significant sources of additional thread-level parallelism, especially for irregular applications that are hard to parallelize by conventio...
Carlos García Quiñones, Carlos Madri...
FPL
2009
Springer
82views Hardware» more  FPL 2009»
15 years 2 months ago
Program-driven fine-grained power management for the reconfigurable mesh
The reconfigurable mesh model for massively parallel computing has recently been rediscovered and proposed as the basis of a practical many-core architecture. With this paper, we...
Heiner Giefers, Marco Platzner