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ICCAD
1992
IEEE
93views Hardware» more  ICCAD 1992»
15 years 1 months ago
Timing analysis in high-level synthesis
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
Andreas Kuehlmann, Reinaldo A. Bergamaschi
CONCUR
2006
Springer
15 years 1 months ago
A Livelock Freedom Analysis for Infinite State Asynchronous Reactive Systems
We describe an incomplete but sound and efficient livelock freedom test for infinite state asynchronous reactive systems. The method s a system into a set of simple control flow cy...
Stefan Leue, Alin Stefanescu, Wei Wei
SIGMETRICS
1999
ACM
130views Hardware» more  SIGMETRICS 1999»
15 years 1 months ago
Address Trace Compression Through Loop Detection and Reduction
ded Abstract This paper introduces a new technique for compressing memory address traces. The technique relies on the simple observation that most programs spend their time execut...
E. N. Elnozahy
ESEM
2007
ACM
15 years 1 months ago
A Critical Analysis of Empirical Research in Software Testing
In the foreseeable future, software testing will remain one of the best tools we have at our disposal to ensure software dependability. Empirical studies are crucial to software t...
Lionel C. Briand
VEE
2012
ACM
255views Virtualization» more  VEE 2012»
13 years 5 months ago
Adding dynamically-typed language support to a statically-typed language compiler: performance evaluation, analysis, and tradeof
Applications written in dynamically typed scripting languages are increasingly popular for Web software development. Even on the server side, programmers are using dynamically typ...
Kazuaki Ishizaki, Takeshi Ogasawara, José G...