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ICCAD
2006
IEEE
112views Hardware» more  ICCAD 2006»
15 years 6 months ago
A new RLC buffer insertion algorithm
Most existing buffering algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches...
Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weip...
DAC
2009
ACM
15 years 4 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
TACAS
2009
Springer
109views Algorithms» more  TACAS 2009»
15 years 4 months ago
TaPAS: The Talence Presburger Arithmetic Suite
TAPAS is a suite of libraries dedicated to FO (R, Z, +, ≤). The suite provides (1) the application programming interface GENEPI for this logic with encapsulations of many classic...
Jérôme Leroux, Gérald Point
FOCS
2009
IEEE
15 years 4 months ago
Reducibility among Fractional Stability Problems
— In a landmark paper [32], Papadimitriou introduced a number of syntactic subclasses of TFNP based on proof styles that (unlike TFNP) admit complete problems. A recent series of...
Shiva Kintali, Laura J. Poplawski, Rajmohan Rajara...
GLOBECOM
2009
IEEE
15 years 4 months ago
Sparse Decoding of Low Density Parity Check Codes Using Margin Propagation
—One of the key factors underlying the popularity of Low-density parity-check (LDPC) code is its iterative decoding algorithm that is amenable to efficient hardware implementati...
Ming Gu, Kiran Misra, Hayder Radha, Shantanu Chakr...