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» UMDAs for dynamic optimization problems
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72
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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
15 years 7 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
SOSP
2009
ACM
15 years 7 months ago
The multikernel: a new OS architecture for scalable multicore systems
Commodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instructio...
Andrew Baumann, Paul Barham, Pierre-Évarist...
91
Voted
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
15 years 7 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
96
Voted
BIRTHDAY
2009
Springer
15 years 5 months ago
Vertical Object Layout and Compression for Fixed Heaps
Research into embedded sensor networks has placed increased focus on the problem of developing reliable and flexible software for microcontroller-class devices. Languages such as ...
Ben Titzer, Jens Palsberg
113
Voted
INFOCOM
2009
IEEE
15 years 4 months ago
Coalitional Games for Distributed Collaborative Spectrum Sensing in Cognitive Radio Networks
— Collaborative spectrum sensing among secondary users (SUs) in cognitive networks is shown to yield a significant performance improvement. However, there exists an inherent tra...
Walid Saad, Zhu Han, Mérouane Debbah, Are H...