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EVOW
2001
Springer
15 years 1 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
15 years 1 months ago
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
ATS
2009
IEEE
132views Hardware» more  ATS 2009»
15 years 4 months ago
On Improving Diagnostic Test Generation for Scan Chain Failures
In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-...
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. ...
EDM
2009
179views Data Mining» more  EDM 2009»
14 years 7 months ago
Learning Factors Transfer Analysis: Using Learning Curve Analysis to Automatically Generate Domain Models
This paper describes a novel method to create a quantitative model of an educational content domain of related practice item-types using learning curves. By using a pairwise test t...
Philip I. Pavlik Jr., Hao Cen, Kenneth R. Koedinge...
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
15 years 2 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi