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ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
15 years 3 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...
DAC
2007
ACM
15 years 10 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
ITC
1992
IEEE
76views Hardware» more  ITC 1992»
15 years 1 months ago
A Small Test Generator for Large Designs
In this paper we report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. t...
Sandip Kundu, Leendert M. Huisman, Indira Nair, Vi...
TCAD
2002
106views more  TCAD 2002»
14 years 9 months ago
Design of hierarchical cellular automata for on-chip test pattern generator
This paper introduces the concept of hierarchical cellular automata (HCA). The theory of HCA is developed over the Galois extension field (2 ), where each cell of the CA can store ...
Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaud...
FORTE
1998
14 years 10 months ago
Fault-oriented Test Generation for Multicast Routing Protocol Design
Abstract: We present a new algorithm for automatic test generation for multicast routing. Our algorithm processes a nite state machine (FSM) model of the protocol and uses a mix of...
Ahmed Helmy, Deborah Estrin, Sandeep K. S. Gupta