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ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
15 years 1 months ago
Improving coverage analysis and test generation for large designs
State space techniques have proven to be useful for measuring and improving the coverage of test vectors that are used during functional validation via simulation. By comparing th...
Jules P. Bergmann, Mark Horowitz
DSD
2008
IEEE
115views Hardware» more  DSD 2008»
15 years 3 months ago
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
We propose a method to efficiently design a “parity generator”, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designe...
Petr Fiser, Pavel Kubalík, Hana Kubatova
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
15 years 3 months ago
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Rui Rodrigues, João M. P. Cardoso
75
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CSB
2003
IEEE
15 years 2 months ago
Group Testing With DNA Chips: Generating Designs and Decoding Experiments
DNA microarrays are a valuable tool for massively parallel DNA-DNA hybridization experiments. Currently, most applications rely on the existence of sequence-specific oligonucleot...
Alexander Schliep, David C. Torney, Sven Rahmann
ATS
2000
IEEE
86views Hardware» more  ATS 2000»
15 years 1 months ago
An adjacency-based test pattern generator for low power BIST design
Patrick Girard, Loïs Guiller, Christian Landr...