Sciweavers

872 search results - page 9 / 175
» UML-based design test generation
Sort
View
VLSID
2003
IEEE
96views VLSI» more  VLSID 2003»
15 years 9 months ago
Design Of A Universal BIST (UBIST) Structure
This paper introduces a Built-In Self Test (BIST) structure referred to as Universal BIST (UBIST). The Test Pattern Generator (TPG) of the proposed UBIST is designed to generate an...
Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Pari...
ICST
2009
IEEE
14 years 7 months ago
Putting Formal Specifications under the Magnifying Glass: Model-based Testing for Validation
A software development process is conceptually an abstract form of model transformation, starting from an enduser model of requirements, through to a system model for which code c...
Emine G. Aydal, Richard F. Paige, Mark Utting, Jim...
GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra
DAC
1999
ACM
15 years 10 months ago
A Study in Coverage-Driven Test Generation
Mike Benjamin, Daniel Geist, Alan Hartman, G&eacut...
112
Voted
IFIP
2001
Springer
15 years 1 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre