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ICCAD
1995
IEEE
144views Hardware» more  ICCAD 1995»
15 years 9 months ago
Background memory management for dynamic data structure intensive processing systems
Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...
Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wu...
ICS
1995
Tsinghua U.
15 years 9 months ago
Idiom Recognition in the Polaris Parallelizing Compiler
The elimination of induction variables and the parallelization of reductions in FORTRAN programs have been shown to be integral to performance improvement on parallel computers 7,...
William M. Pottenger, Rudolf Eigenmann
ISCA
1995
IEEE
147views Hardware» more  ISCA 1995»
15 years 9 months ago
Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
Alvin R. Lebeck, David A. Wood
ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
15 years 9 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels
169
Voted
LCPC
1995
Springer
15 years 9 months ago
Compiler Architectures for Heterogeneous Systems
Heterogeneous parallel systems incorporate diverse models of parallelism within a single machine or across machines and are better suited for diverse applications 25, 43, 30]. Thes...
Kathryn S. McKinley, Sharad Singhai, Glen E. Weave...
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