76 search results - page 6 / 16 » Ultra-low power digital subthreshold logic circuits |
87
Voted
TVLSI
2002
14 years 9 months ago
2002
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
82
Voted
DAC
2004
ACM
15 years 1 months ago
2004
ACM
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...
PATMOS
2005
Springer
15 years 3 months ago
2005
Springer
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
ISCAS
2007
IEEE
15 years 4 months ago
2007
IEEE
– In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circu...
ICCAD
2008
IEEE
15 years 7 months ago
2008
IEEE
—To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nanoelect...