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124
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ICCD
2007
IEEE
157views Hardware» more  ICCD 2007»
16 years 27 days ago
Limits on voltage scaling for caches utilizing fault tolerant techniques
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M...
CHARME
2001
Springer
162views Hardware» more  CHARME 2001»
15 years 7 months ago
Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking
We consider the formal verification of the cache coherence protocol of the Stanford FLASH multiprocessor for N processors. The proof uses the SMV proof assistant, a proof system ba...
Kenneth L. McMillan
128
Voted
SYRCODIS
2008
95views Database» more  SYRCODIS 2008»
15 years 5 months ago
The Framework for Study Of Caching Algorithm Efficiency
In this paper we offer several models of reference sequences (traces of references) using Markov chains for testing of the replacement policies in caching systems. These models en...
Michael V. Grankov, Ngo Thanh Hung, Mosab Bassam Y...
BNCOD
2009
97views Database» more  BNCOD 2009»
15 years 5 months ago
An XML-Based Model for Supporting Context-Aware Query and Cache Management
Abstract. Database systems (DBSs) can play an essential role in facilitating the query and cache management in context-aware mobile information systems (CAMIS). Two of the fundamen...
Essam Mansour, Hagen Höpfner
EUROSYS
2007
ACM
16 years 1 months ago
Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
David K. Tam, Reza Azimi, Michael Stumm