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HPCA
2001
IEEE
16 years 4 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
INFOCOM
2002
IEEE
15 years 9 months ago
Using the Small-World Model to Improve Freenet Performance
– Efficient data retrieval in a peer-to-peer system like Freenet is a challenging problem. In this paper we study the impact of cache replacement policy on the performance of Fre...
Hui Zhang 0002, Ashish Goel, Ramesh Govindan
SIGMOD
2000
ACM
98views Database» more  SIGMOD 2000»
15 years 8 months ago
High Speed On-line Backup When Using Logical Log Operations
Media recovery protects a database from failures of the stable medium by maintaining an extra copy of the database, called the backup, and a media recovery log. When a failure occ...
David B. Lomet
MICRO
1997
IEEE
141views Hardware» more  MICRO 1997»
15 years 8 months ago
Unroll-and-Jam Using Uniformly Generated Sets
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
Steve Carr, Yiping Guan
EDBT
2010
ACM
155views Database» more  EDBT 2010»
15 years 7 months ago
Suffix tree construction algorithms on modern hardware
Suffix trees are indexing structures that enhance the performance of numerous string processing algorithms. In this paper, we propose cache-conscious suffix tree construction algo...
Dimitris Tsirogiannis, Nick Koudas