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HPCA
2012
IEEE
13 years 11 months ago
SCD: A scalable coherence directory with flexible sharer set encoding
Large-scale CMPs with hundreds of cores require a directory-based protocol to maintain cache coherence. However, previously proposed coherence directories are hard to scale beyond...
Daniel Sanchez, Christos Kozyrakis
126
Voted
ISCA
2005
IEEE
121views Hardware» more  ISCA 2005»
15 years 9 months ago
Direct Cache Access for High Bandwidth Network I/O
Recent I/O technologies such as PCI-Express and 10Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory ...
Ram Huggahalli, Ravi R. Iyer, Scott Tetrick
GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
15 years 9 months ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
ISCA
1991
IEEE
162views Hardware» more  ISCA 1991»
15 years 7 months ago
Comparison of Hardware and Software Cache Coherence Schemes
We use mean value analysis models to compare representative hardware and software cache coherence schemes for a large-scale shared-memory system. Our goal is to identify the workl...
Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary...
JOC
2010
92views more  JOC 2010»
14 years 11 months ago
Efficient Cache Attacks on AES, and Countermeasures
We describe several software side-channel attacks based on inter-process leakage through the state of the CPU's memory cache. This leakage reveals memory access patterns, whic...
Eran Tromer, Dag Arne Osvik, Adi Shamir