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160
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SIGMETRICS
2003
ACM
199views Hardware» more  SIGMETRICS 2003»
15 years 8 months ago
Data cache locking for higher program predictability
Caches have become increasingly important with the widening gap between main memory and processor speeds. However, they are a source of unpredictability due to their characteristi...
Xavier Vera, Björn Lisper, Jingling Xue
ISCA
2000
IEEE
107views Hardware» more  ISCA 2000»
15 years 8 months ago
A fully associative software-managed cache design
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
Erik G. Hallnor, Steven K. Reinhardt
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 8 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
125
Voted
ICCD
2008
IEEE
117views Hardware» more  ICCD 2008»
16 years 14 days ago
RMA: A Read Miss-Based Spin-Down Algorithm using an NV cache
—It is an important issue to reduce the power consumption of a hard disk that takes a large amount of computer system’s power. As a new trend, an NV cache is used to make a dis...
Hyotaek Shim, Jaegeuk Kim, Dawoon Jung, Jin-Soo Ki...
137
Voted
GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
15 years 10 months ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...