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137
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HIPEAC
2007
Springer
15 years 9 months ago
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
Sonia López, Steve Dropsho, David H. Albone...
157
Voted
ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
15 years 7 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
132
Voted
ECRTS
2008
IEEE
15 years 10 months ago
WCET-driven Cache-based Procedure Positioning Optimizations
Procedure Positioning is a well known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of procedures calling each other freq...
Paul Lokuciejewski, Heiko Falk, Peter Marwedel
121
Voted
ISCA
1996
IEEE
103views Hardware» more  ISCA 1996»
15 years 7 months ago
Evaluation of Design Alternatives for a Multiprocessor Microprocessor
In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor microprocessors. In this paper we consider ...
Basem A. Nayfeh, Lance Hammond, Kunle Olukotun
130
Voted
WSC
1998
15 years 4 months ago
A Speculation-based Approach for Performance and Dependability Analysis: A Case Study
In this paper, we propose two speculation-based methods for fast and accurate simulation-based performance and dependability analysis of complex systems, incorporating detailed si...
Yiqing Huang, Zbigniew Kalbarczyk, Ravishankar K. ...