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144
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ISSS
1996
IEEE
125views Hardware» more  ISSS 1996»
15 years 7 months ago
Size-Constrained Code Placement for Cache Miss Rate Reduction
In design of an embedded system with a cache, it is important to minimize the cache miss rate to reduce the power consumption as well as to improvethe performance of the system. W...
Hiroyuki Tomiyama, Hiroto Yasuura
109
Voted
FAST
2010
15 years 6 months ago
Extending SSD Lifetimes with Disk-Based Write Caches
We present Griffin, a hybrid storage device that uses a hard disk drive (HDD) as a write cache for a Solid State Device (SSD). Griffin is motivated by two observations: First, HDD...
Gokul Soundararajan, Vijayan Prabhakaran, Mahesh B...
145
Voted
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
15 years 10 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
121
Voted
DATE
2008
IEEE
155views Hardware» more  DATE 2008»
15 years 10 months ago
Comparison of memory write policies for NoC based Multicore Cache Coherent Systems
The following study shows a direct comparison of memory write policies in Shared Memory Multicore Systems. Although there are much work and many studies about this issue, our work...
Pierre Guironnet de Massas, Frédéric...
156
Voted
NPC
2005
Springer
15 years 9 months ago
Adaptive Query-Caching in Peer-to-Peer Systems
Peer-to-Peer (P2P) architectures are very prevalent in today’s Internet. Lots of P2P file sharing systems using Gnutella protocol emerge out and draw attractions of millions of p...
Zuoning Yin, Hai Jin, Chao Zhang, Quan Yuan, Chuch...