Sciweavers

1872 search results - page 98 / 375
» Unbalanced Cache Systems
Sort
View
156
Voted
ECRTS
2008
IEEE
15 years 10 months ago
Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
IPPS
1999
IEEE
15 years 8 months ago
Linear Aggressive Prefetching: A Way to Increase the Performance of Cooperative Caches
Cooperative caches offer huge amounts of caching memory that is not always used as well as it could be. We might find blocks in the cache that have not been requested for many hou...
Toni Cortes, Jesús Labarta
183
Voted
HIPEAC
2011
Springer
14 years 3 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
16 years 20 days ago
Energy Characterization of Hardware-Based Data Prefetching
This paper evaluates several hardware-based data prefetching techniques from an energy perspective, and explores their energy/performance tradeoffs. We present detailed simulation...
Yao Guo, Saurabh Chheda, Israel Koren, C. Mani Kri...
204
Voted
DATE
2011
IEEE
223views Hardware» more  DATE 2011»
14 years 7 months ago
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
Martin Schoeberl, Pascal Schleuniger, Wolfgang Puf...