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» Uncertainty Reduction Using Dynamics
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CODES
2007
IEEE
15 years 7 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
130
Voted
ASIACRYPT
2010
Springer
14 years 10 months ago
Random Oracles with(out) Programmability
This paper investigates the Random Oracle Model (ROM) feature known as programmability, which allows security reductions in the ROM to dynamically choose the range points of an ide...
Marc Fischlin, Anja Lehmann, Thomas Ristenpart, Th...
99
Voted
KDD
2004
ACM
138views Data Mining» more  KDD 2004»
16 years 1 months ago
IDR/QR: an incremental dimension reduction algorithm via QR decomposition
Dimension reduction is a critical data preprocessing step for many database and data mining applications, such as efficient storage and retrieval of high-dimensional data. In the ...
Jieping Ye, Qi Li, Hui Xiong, Haesun Park, Ravi Ja...
118
Voted
TPDS
2010
174views more  TPDS 2010»
14 years 11 months ago
Parallel Two-Sided Matrix Reduction to Band Bidiagonal Form on Multicore Architectures
The objective of this paper is to extend, in the context of multicore architectures, the concepts of tile algorithms [Buttari et al., 2007] for Cholesky, LU, QR factorizations to t...
Hatem Ltaief, Jakub Kurzak, Jack Dongarra
ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
15 years 9 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...