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» Uncertainty-aware circuit optimization
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116
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VLSID
2008
IEEE
153views VLSI» more  VLSID 2008»
16 years 4 months ago
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation
Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. Howeve...
Yuanlin Lu, Vishwani D. Agrawal
ICCAD
2001
IEEE
102views Hardware» more  ICCAD 2001»
16 years 14 days ago
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...
101
Voted
ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
15 years 10 months ago
Running a Quantum Circuit at the Speed of Data
We analyze circuits for a number of kernels from popular quantum computing applications, characterizing the hardware resources necessary to take ancilla preparation off the critic...
Nemanja Isailovic, Mark Whitney, Yatish Patel, Joh...
121
Voted
ISCAS
2007
IEEE
94views Hardware» more  ISCAS 2007»
15 years 10 months ago
Run-Time Programming of Analog Circuits Using Floating-Gate Transistors
— The ability to recalibrate a system is an important feature in allowing that system to maintain optimal performance even in the face of new demands placed on that system by env...
David W. Graham, Paul E. Hasler
153
Voted
ASPDAC
2006
ACM
117views Hardware» more  ASPDAC 2006»
15 years 9 months ago
Signal-path driven partition and placement for analog circuit
This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three...
Di Long, Xianlong Hong, Sheqin Dong