1217 search results - page 113 / 244 » Uncertainty-aware circuit optimization |
ENGL
2008
14 years 11 months ago
2008
This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated Annealing (SA). The proposed architecture achieves ...
110
click to vote
CASES
2011
ACM
13 years 11 months ago
2011
ACM
Escalating variations in modern CMOS designs have become a threat to Moore’s law. While previous works have proposed techniques for tolerating variations by trading reliability ...
VLSID
1993
IEEE
15 years 3 months ago
1993
IEEE
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
DAC
1994
ACM
15 years 3 months ago
1994
ACM
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...
100
click to vote
GLVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...