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» Uncertainty-aware circuit optimization
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ICCD
2000
IEEE
79views Hardware» more  ICCD 2000»
15 years 8 months ago
Efficient Logic Optimization Using Regularity Extraction
This paper presents a new method to extract functionally equivalent structures from logic netlists. It uses a fast functional regularity extraction algorithm based on structural e...
Thomas Kutzschebauch
ICCAD
2005
IEEE
100views Hardware» more  ICCAD 2005»
15 years 8 months ago
Performance-centering optimization for system-level analog design exploration
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih C...
ASPDAC
2010
ACM
112views Hardware» more  ASPDAC 2010»
14 years 9 months ago
Optimizing blocks in an SoC using symbolic code-statement reachability analysis
Abstract-- Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused d...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Node Mergers in the Presence of Don't Cares
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Vale...
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
15 years 5 months ago
Area optimization of multi-cycle operators in high-level synthesis
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
María C. Molina, Rafael Ruiz-Sautua, Jose M...