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1217
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Uncertainty-aware circuit optimization
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ICCAD
1993
IEEE
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Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
15 years 7 months ago
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Kerry S. Lowe, P. Glenn Gulak
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DAC
1993
ACM
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Computer Architecture
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Optimization of Combinational Logic Circuits Based on Compatible Gates
15 years 7 months ago
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Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni D...
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80
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DAC
1992
ACM
86
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Computer Architecture
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DAC 1992
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The Role of Long and Short Paths in Circuit Performance Optimization
15 years 7 months ago
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acadepedia.com
Siu-Wing Cheng, Hsi-Chuan Chen, David Hung-Chang D...
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106
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DAC
1992
ACM
100
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Computer Architecture
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DAC 1992
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Recurrence Equations and the Optimization of Synchronous Logic Circuits
15 years 7 months ago
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Maurizio Damiani, Giovanni De Micheli
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ASPDAC
2007
ACM
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ASPDAC 2007
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Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation
15 years 7 months ago
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Cheoljoo Jeong, Steven M. Nowick
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