1217 search results - page 124 / 244 » Uncertainty-aware circuit optimization |
ICCAD
2003
IEEE
15 years 4 months ago
2003
IEEE
This paper presents several important enhancements to the recently published multilevel placement package mPL [12]. The improvements include (i) unconstrained quadratic relaxation...
ASPDAC
2006
ACM
15 years 5 months ago
2006
ACM
− In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed th...
GLVLSI
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
ICCAD
2005
IEEE
15 years 8 months ago
2005
IEEE
Separate optimizations of logic and layout have been thoroughly studied in the past and are well documented for common benchmarks. However, to be competitive, modern circuit optim...
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DAC
2004
ACM
16 years 12 days ago
2004
ACM
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...