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» Uncertainty-aware circuit optimization
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DATE
2004
IEEE
131views Hardware» more  DATE 2004»
15 years 3 months ago
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive differe...
Anuja Sehgal, Krishnendu Chakrabarty
EUROPAR
2000
Springer
15 years 3 months ago
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations
We present a compiler algorithm called BitValue, which can discover both unused and constant bits in dusty-deck C programs. BitValue uses forward and backward dataflow analyses, ge...
Mihai Budiu, Majd Sakr, Kip Walker, Seth Copen Gol...
DAC
1995
ACM
15 years 3 months ago
New Performance-Driven FPGA Routing Algorithms
—Motivated by the goal of increasing the performance of FPGA-based designs, we propose new Steiner and arborescence FPGA routing algorithms. Our Steiner tree constructions signiï...
Michael J. Alexander, Gabriel Robins
AAAI
2008
15 years 1 months ago
Generating Application-Specific Benchmark Models for Complex Systems
Automated generators for synthetic models and data can play a crucial role in designing new algorithms/modelframeworks, given the sparsity of benchmark models for empirical analys...
Jun Wang, Gregory M. Provan
ASPDAC
2008
ACM
150views Hardware» more  ASPDAC 2008»
15 years 1 months ago
Constraint-free analog placement with topological symmetry structure
Abstract-- In analog circuits, blocks need to be placed symmetrically to satisfy the devices matching. Different from the existing constraint-driven approaches, the proposed topolo...
Qing Dong, Shigetoshi Nakatake