1217 search results - page 136 / 244 » Uncertainty-aware circuit optimization |
DAC
2001
ACM
16 years 18 days ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We sh...
101
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ISVLSI
2007
IEEE
15 years 6 months ago
2007
IEEE
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
116
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INFOCOM
2006
IEEE
15 years 5 months ago
2006
IEEE
— Gupta and Kumar showed that throughput in a static random wireless network increases with the amount of hopping. In a subsequent paper (2004), it was shown that although throug...
ASIACRYPT
2001
Springer
15 years 4 months ago
2001
Springer
Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all...