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» Uncertainty-aware circuit optimization
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ARVLSI
1999
IEEE
94views VLSI» more  ARVLSI 1999»
15 years 4 months ago
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
Ayoob E. Dooply, Kenneth Y. Yun
ICCAD
2009
IEEE
94views Hardware» more  ICCAD 2009»
14 years 9 months ago
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...
CASES
2010
ACM
14 years 8 months ago
Optimizing energy to minimize errors in dataflow graphs using approximate adders
Approximate arithmetic is a promising, new approach to lowenergy designs while tackling reliability issues. We present a method to optimally distribute a given energy budget among...
Zvi M. Kedem, Vincent John Mooney, Kirthi Krishna ...
TCAD
2010
107views more  TCAD 2010»
14 years 6 months ago
Evaluating Statistical Power Optimization
In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this ...
Jason Cong, Puneet Gupta, John Lee
ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
15 years 8 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...