1217 search results - page 139 / 244 » Uncertainty-aware circuit optimization |
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at...
103
Voted
ARITH
2003
IEEE
15 years 5 months ago
2003
IEEE
Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF(2m ) which has a low hardware complexity and a low latenc...
80
Voted
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
70
Voted
TCAD
1998
14 years 11 months ago
1998
—This paper introduces a novel optimization paradigm for increasing the throughput of digital systems. The basic idea consists of transforming fixed-latency units into variable-...
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
As technology enters the nanometer territory, the antenna effect plays an important role in determining the yield and reliability of a VLSI circuit. Diode insertion and jumper in...