1217 search results - page 141 / 244 » Uncertainty-aware circuit optimization |
82
Voted
HPCC
2009
Springer
14 years 9 months ago
2009
Springer
Domain-partition (DP) model is a general model for reliability maximization problem under given redundancy. In this paper, an improved DP model is used to formulate a reconfigurati...
113
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ICCAD
2009
IEEE
14 years 9 months ago
2009
IEEE
Clock skew scheduling has been effectively used to reduce the clock period of sequential circuits. However, this technique may become impractical if a different skew must be appli...
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
ICCAD
2008
IEEE
15 years 8 months ago
2008
IEEE
—Connecting system-level performance models with circuit information has been a long-standing problem in analog/mixed-signal front-ends, like radios and high-speed links. High-sp...
88
Voted
ICCAD
2008
IEEE
15 years 8 months ago
2008
IEEE
- In this paper, we present a technique to optimize the energy-delay product of a synchronous linear pipeline circuit with dynamic error detection and correction capability running...