1217 search results - page 153 / 244 » Uncertainty-aware circuit optimization |
143
Voted
FPGA
2010
ACM
16 years 13 days ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
123
Voted
IMR
2004
Springer
15 years 9 months ago
2004
Springer
This paper presents a generic approach to mesh global optimization via node movement, based on a discrete graph-theoretic model. Mesh is considered as an electric system with lump...
123
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ICCAD
2003
IEEE
16 years 14 days ago
2003
IEEE
This work studies the optimality and stability of timing-driven placement algorithms. The contributions of this work include two parts: 1) We develop an algorithm for generating s...
150
Voted
ICCAD
1999
IEEE
15 years 7 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
131
Voted
TCAD
2010
14 years 10 months ago
2010
Abstract--In sub-100 nm CMOS processes, delay and leakage power reduction continue to be among the most critical design concerns. We propose to exploit the recent availability of f...