1217 search results - page 155 / 244 » Uncertainty-aware circuit optimization |
134
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ISQED
2002
IEEE
15 years 8 months ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
153
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VLSID
2002
IEEE
15 years 8 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
120
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DAC
2003
ACM
16 years 4 months ago
2003
ACM
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...
107
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ICCD
2008
IEEE
16 years 16 days ago
2008
IEEE
— Circuit and processor designs will continue to increase in complexity for the foreseeable future. With these increasing sizes comes the use of wide buses to move large amounts ...
101
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ICCAD
2007
IEEE
16 years 14 days ago
2007
IEEE
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...