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» Uncertainty-aware circuit optimization
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141
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DAC
2008
ACM
16 years 4 months ago
Path smoothing via discrete optimization
A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can als...
Michael D. Moffitt, David A. Papa, Zhuo Li, Charle...
122
Voted
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
16 years 4 months ago
Statistical Leakage and Timing Optimization for Submicron Process Variation
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
Yuanlin Lu, Vishwani D. Agrawal
121
Voted
IPPS
2006
IEEE
15 years 9 months ago
An optimal architecture for a DDC
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...
120
Voted
SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
15 years 9 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
120
Voted
ISQED
2003
IEEE
109views Hardware» more  ISQED 2003»
15 years 9 months ago
Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers
Abstract- This paper presents a detailed empirical study and analytical derivation of voltage wave-form and energy dissipation of global lines driven by CMOS drivers. It is shown t...
Soroush Abbaspour, Massoud Pedram, Payam Heydari